----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:52:42 10/12/2011 
-- Design Name: 
-- Module Name:    TeleTexto - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TeleTexto is
    Port ( 
	        clk, reset: in std_logic;
			  datos_a_enviar : in  STD_LOGIC_VECTOR (7 downto 0);
           fifo_llena : in  STD_LOGIC;
           fifo_vacia : in  STD_LOGIC;
			  estado : in STD_LOGIC_VECTOR ( 3 downto 0);
			  href_neg : in STD_LOGIC;
			  ---Salidas
           mi_dato : out  STD_LOGIC_VECTOR (7 downto 0));
			  
end TeleTexto;

architecture Behavioral of TeleTexto is


 --Codificacion

-- "00001001"  --> 9		fifo llena
-- "00001010"  --> 10	fifo vacia
begin
	
	



	
	process(clk,href_neg)
	begin
		if ( href_neg ='1' ) then
			mi_dato <= "00000001";
		else			
			mi_dato<=datos_a_enviar;
		end if;
	end process;
	
	
	
--	process(clk,fifo_llena,fifo_vacia,estado)
--		begin
--		
--		if (fifo_llena='1')then
--			mi_dato<="00001000";
--		elsif (fifo_vacia='1')then
--			mi_dato<="00001010";
--		elsif (fifo_vacia='1' and fifo_llena='1') then
--			mi_dato <= "00000011";
--		elsif ( fifo_vacia='0' and fifo_llena='0')then -- Seguimiento estados
--			mi_dato <= "0000"&estado;
--			
--		
--		else
--			mi_dato<=datos_a_enviar;
--		end if;
--		
--	end process;

end Behavioral;


-- Mi teletecto
--TeleTexto: entity TeleTexto
--   port map(
--    clk   =>,
--		reset =>,
--    --in
--    datos_a_enviar   =>,
--    fifo_llena   =>,
--    fifo_vacia   =>,


--    --Out
--		mi_dato   =>

--
--   );
